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Cypress Semiconductor /psoc63 /BLE /BLESS /EFUSE_TIM_CTRL2

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Interpret as EFUSE_TIM_CTRL2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DATA_SAMPLE_TIME0DOUT_CS_HOLD_TIME

Description

EFUSE timing control Register (for Read)

Fields

DATA_SAMPLE_TIME

This register specifies the time for data sampling from SCLK HIGH (TCKDQ_H)
DOUT_CS_HOLD_TIME

Wait time DOUT to CS hold time out of read mode (TDQH)

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data